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About the course :
Globalization and Technology have compelled nations to open up their economies to global competition. In India too, new economic initiatives by the Govt. have encouraged significant global orientation. Indian industry is evaluating and rapidly consolidating its strengths. It is now established that Indian Software and hardware industry has tremendous potential for growth. DSP (Digital Signal Processing) is the field of future & real time processing is need of the hour.

This course is aimed at developing DSP based system using VLSI. The concept will be introduced by eminent personalities. Extensive practical & hands on experience will be given. The exit level of participants would be a clear understanding of best of industry practices in the field of DSP.
 
The course objectives
  • Familiarized participants with DSP system design building blocks & processing requirement
  • Knowledge of Xilinx ISE Design flow, Matlab & Simulink Design Flow, System generator design flow.
  • Familiarization with SP-III trainer board & hardware of board
  • DSP algorithm implementation in FPGA/ SP-III Trainer board using System generator
  • Discussion on issue related to implementation of DSP algorithm on various FPGA architectures.
 
Eligibility
Faculties from all Aided and Non-aided Technical Institutions.

Prerequisites
The desirable participants should have some of the fundamental knowledge in the field mentioned below:
  • Basic DSP
  • Basics of VHDL & Xilinx
Note: Participants will be receiving soft copy of course contents after confirmation, on e-mail
 
Course contents
Day 1:
  • Basic terminology & acronyms used in DSP
  • Sampling, sampling rate & bit widths used in DSP applications
  • Minimum maximum sampling rate concept
  • Effect due to low sampling rate, Aliasing, practical limitation in maximum sampling rate.
  • Reconstruction, quantization & its effect on DSP
  • DSP building blocks & processing requirements of DSP
  • Time domain & frequency analysis
 
Day 2:
  • Implementing the multiplication function
  • Bit width impact on system level decision
  • CORE generator function & capabilities
  • Delay, MAC, Tree adder multiplier architecture
  • Frequency leakage , windowing
  • Numeric controlled oscillators & mixers.
 
Day 3:
  • FIR filter design, windowing
  • FIR filter specification & implementation
  • Multirate signal processing